Analog Design Architect and Technical Lead

Job title:

Analog Design Architect and Technical Lead

Company

Ciena

Job description

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.Why Ciena?

• We’re a company rooted in people—seeking to create a vibrant and inclusive environment, where everyone feels they can belong.
• Accelerate your career path by gaining hands-on experience and exposure to the latest technology. Our interns and graduates work on real projects in real time in world class labs. Be a part of tomorrow’s future – today.

• Mentoring. Networking. Leadership Opportunities. We recognize that the learning doesn’t stop when you leave school – we champion a team environment for development and provide the tools to achieve success.
• We are big proponents of life-work integration. Our people make a big difference at Ciena, but we want to shine light on their differences outside of working hours too. CienaCares supports non-profit causes important to employees by matching employee financial contributions and dedicating time for volunteering.

How You Will Contribute:Ciena is looking for an Analog Design Architect and Technical Lead with experience designing low-jitter high-speed PLLs as well as precision analog circuits such as bandgaps, reference generators, and LDOs. Reporting to the Director of Analog Engineering responsible for clocking and power management, you will play a key role as you will be responsible for the architecture, design, and verification of high-speed extremely low jitter PLLs as well as precision analog circuits servicing high-speed serial interfaces for both electrical and optical links on leading-edge CMOS process technology nodes such as 3nm and below. This role also has a team building aspect and can lead to a management position as it is expected that a group responsible for high-speed clocking and power management for next generation SerDes will be formed.Responsibilities

• Provide recommendations on circuit architecture showing tradeoffs of different schemes.
• Lead the development and directly participate in the design of circuits in 3nm or below CMOS technology to build various blocks of the design.
• Perform detailed simulations (SPICE and/or mixed-signal) to verify that the circuit solutions will meet the required specifications.
• Provide technical advice and assistance to more junior engineers on the team to guide their success.
• Help growing and scaling the team.
• Interface with DSP, digital, system, link and package engineering groups.
• Provide clear written updates to management on the progress of the work, any issues that are found and the overall schedule.
• Monitoring of industry standards and alerting senior management of potential roadblocks in product development
• Test, debug and characterization of prototypes in the lab.

The Must Haves:

• BS /Master/ PhD degree or experience in Electrical Engineering or another technical related field.
• Direct hands-on experience in the field of high-speed serial interface design in CMOS of at least 10 years.
• Solid knowledge of integrated circuit design, device physics and advanced process technology.
• Experience in designing PLLs and its various building blocks such as VCOs, phase detectors, charge pumps, high-speed clock buffers, frequency dividers, analog and digital filters, and other related circuits.
• Experience in designing bandgaps, bias generation, op-amps, LDOs, feedback and compensation techniques as well as digitally assisted analog circuit techniques.
• Deep understanding of transistor modeling, circuit noise theory and phase noise concepts.
• Proficient in Cadence analog / mixed signal simulation toolset.
• Familiar with Analog/Mixed Signal design flow, simulation models, design rules, verification procedures (DRC/LVS/ERC), and transistor-level simulations.

Assets:

• Excellent communication, interpersonal and team building skills.

Compensation and BenefitsThe annual pay range for this position is $127,700 – $204,100 CAD.Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.Not ready to apply? Join our to get relevant job alerts straight to your inbox.At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.Ciena is an Equal Opportunity Employer, including disability and protected veteran status.If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Expected salary

Location

Ottawa, ON

Job date

Wed, 11 Dec 2024 05:52:06 GMT

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