Design Verification Engineer

Job title:

Design Verification Engineer

Firm

Superior Micro Gadgets

Job description

Job Description:WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about reworking lives with AMD know-how to counterpoint our business, our communities, and the world. Our mission is to construct nice merchandise that speed up next-generation computing experiences – the constructing blocks for the info heart, synthetic intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD tradition. We push the boundaries of innovation to unravel the world’s most essential challenges. We attempt for execution excellence whereas being direct, humble, collaborative, and inclusive of numerous views.AMD collectively we advance_THE ROLE:The AMD IOHUB Crew (a part of the NBIO group) is searching for an ASIC Design Engineer to affix our rising workforce. We develop modern I/O connectivity and virtualization applied sciences powering information heart and machine studying workloads. This workforce is a part of the event for tomorrow’s shopper, server, embedded, graphics, and semi-custom chips. You’ll be concerned in all elements of IP design ranging from structure to necessities to execution.THE PERSONAs a key contributor to the success of AMD’s IP, you’ll be a part of a number one workforce to drive and enhance AMD’s talents to ship the very best high quality, business main applied sciences to market. The NBIO Crew fosters and encourages steady technical innovation to showcase successes in addition to facilitate steady profession improvement.KEY RESPONSIBILITIES:

• Perceive the practical and efficiency necessities of the IOHUB inside varied SOCs
• Drive IP/SOC design infra selections to make sure consumption inside the context of the SOC.
• Present steerage and/or act as a liaison between IP and SOC design groups for synthesis and bodily format points
• Scope necessities and assets to satisfy mission schedules
• Present fingers on management of a small workforce of Engineers/Engineers in Coaching as required to satisfy program improvement objectives
• Signoff IP high quality for supply into SOC
• Successfully talk with multi-disciplined groups positioned throughout the globe
• Collect, attend and current into technical standing conferences on a weekly/bi-weekly foundation

PREFERRED EXPERIENCE:

• Massive ASIC verification expertise

• Confirmed RTL design expertise on giant ASIC improvement tasks
• Robust background working with business customary synthesis instruments, flows and again finish timing closure(e.g. Formality, CDC & Linting instruments, Design Compiler/FX and so on)
• Robust background in Verilog and System Verilog
• Robust analytical expertise and a focus to element
• Glorious written and communication expertise
• Understanding of the IP integration and interactions inside an SOC
• Have to be a self-starter and capable of independently drive duties to completion
• Demonstrates the flexibility to debug points and shortly determine viable options
• Crew participant with confirmed management expertise

ACADEMIC EXPERIENCE:

• Bachelor of Science Diploma in Electrical Engineering, Laptop Science, or Laptop Engineering

LOCATION:

• Vancouver, BC
• Markham, ON

#LI-SL3#HYBRIDAdvantages provided are described: .AMD doesn’t settle for unsolicited resumes from headhunters, recruitment companies, or fee-based recruitment providers. AMD and its subsidiaries are equal alternative, inclusive employers and can take into account all candidates with out regard to age, ancestry, shade, marital standing, medical situation, psychological or bodily incapacity, nationwide origin, race, faith, political and/or third-party affiliation, intercourse, being pregnant, sexual orientation, gender id, navy or veteran standing, or every other attribute protected by regulation. We encourage functions from all certified candidates and can accommodate candidates’ wants below the respective legal guidelines all through all levels of the recruitment and choice course of.

Anticipated wage

Location

Vancouver, BC

Job date

Mon, 08 Apr 2024 22:05:30 GMT

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