Design Verification Engineer

Job title:

Design Verification Engineer

Company

Advanced Micro Devices

Job description

Job Description:WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.AMD together we advance_THE ROLE:AMD is looking for motivated individuals seeking opportunities to solve complex problems in a fast-paced work environment. The successful candidate will be involved in all aspects of AMD’s next generation products. This includes verifying PCI Express/CXL design using latest UVM standard and develop comprehensive test plan to ensure coverage closure. Candidate will also apply low power verification methodology and measure overall system performance of our IP. The position allows exposure to all aspect of ASIC design stages. AMD employee contributions are at the core of our technology solutions. Interested about transforming the world?THE PERSON:

• Creative innovator and thinker who loves technical problems and detail-oriented tasks
• Exhibits relentless commitment to help the team meet quality and development goals on schedule
• Drives to learn and perform at his or her highest potential in a technical capacity
• Thrives in both a team environment and in individual contribution
• Communicates openly and clearly in meetings, presentations, emails, and reports
• Able to learn independently and acquire new skills required for the job
• Flexible in working hours to accommodate working with co-workers in different time-zones

KEY RESPONSIBILITIES:

• Writing/Implementing/Reviewing Test Plans
• Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments
• Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in System Verilog/UVM
• Analyzing Functional, Code, and Test Plan Coverage
• Implementing Assertions, Checkers, and Monitors
• Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification
• Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
• Triaging and Debugging Regressions
• Reproducing Functional Bugs found in Silicon in Simulation and/or Formal Verification tools
• Conducting and participating in Code Reviews
• Technical leadership is an asset, including driving projects from start to the finish and Design verification sign-off

PREFERRED EXPERIENCE:

• Working experience in ASIC is preferred.
• Testbench Architecture, System Verilog, OVM/UVM/VMM
• C/C++, Java, or other object-oriented programming language
• Perl, Ruby, Shell-scripting, UNIX/LINUX Environment
• VCS, NCSIM, Questa, or other simulator and associated waveform viewers such as Verdi
• PC System Architecture: PCI Express, Hyper Transport, x86, ARM
• On-Chip Bus Interfaces and Architectures: AMBA AXI, OCP, PIPE

ACADEMIC CREDENTIALS:

• PhD in Electrical Engineering or Computer Engineering or related equivalent with Or
• Master’s Degree in Electrical Engineering/Computer Engineering/related equivalent Or
• Bachelor’s Degree in Electrical Engineering/Computer Engineering/related equivalent

LOCATION: Vancouver/ Markham/ Ottawa#LI-KG1#LI-HYBRIDBenefits offered are described: .AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Expected salary

Location

Vancouver, BC

Job date

Tue, 09 Apr 2024 04:02:43 GMT

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