Senior/Principal Design Verification Engineer

Job title:

Senior/Principal Design Verification Engineer

Company

lowRISC

Job description

lowRISC CIC Senior/Principal Design Verification EngineerCambridge, UK, Full-time, Permanent, Salary: £62,708 – £96,632 dependent on experienceThe CompanySix years ago, lowRISC (a community interest company) took up the challenge of helping to bring the world’s first commercially viable, collaborative, open source silicon root of trust (RoT) design, OpenTitan, to market. We didn’t want to create a ‘one-and-done monolith’ though – instead, we set out to use the project as the proving ground for our general development framework: the Silicon Commons. This innovative workflow merges open source software development best practices with an industrial-strength chip design methodology, enabling the creation of reusable, high quality silicon IP by our diverse coalition of corporate and academic partners including Google, ETH Zurich, G+D Mobile, Nuvoton, Rivos, Seagate, Western Digital and Winbond.Join us and be part of a company positively changing the future of silicon design.The RoleIn this role you will have the opportunity to apply industrial-strength design verification to high quality open source code bases. We are raising the bar for verification of open source projects to meet the highest commercial standards. Your focus will be on the verification of the range of open source designs we are producing for the future iterations of OpenTitan. This includes a RISC-V core (Ibex), a separate special purpose CPU for cryptographic operations, an AES accelerator and a variety of peripherals (such as USB, I2C and SPI).You will:

• Design, implement and debug block-level and system-level tests and testbenches using SystemVerilog and UVM
• Stay up to date with the latest best practices and bring innovations to lowRISC
• Develop test and coverage plans for new or updated silicon designs
• Actively review contributions to our open source projects
• Triage and debug nightly regressions
• Contribute to the ongoing design and development of our test and continuous integration infrastructure
• Collaborate with partners to author papers for academic and industry conferences

Candidate RequirementsEssential:

• 5 years+ prior industry experience of design verification including significant SystemVerilog and UVM usage
• Experience across the full verification cycle from initial planning to final tape out
• Confident providing work estimates and coordinating work with a project manager
• Comfortable working with engineers across multiple organisations in multidisciplinary teams
• Undergraduate degree in a technical discipline or equivalent experience

Desirable:

• Broad experience range with background across multiple types of hardware blocks
• Understanding of security countermeasures against attacks such as fault injection or side-channel analysis
• Experience working with the RISC-V ISA or other instruction sets
• Familiarity with Git and code review using services such as GitHub, GitLab or Gerrit
• Programming using C and/or Python in tests and automation
• Formal verification with tools such as JasperGold

For the Principal role:

• Experience with leading a team or being a primary technical contributor in a major project

BenefitslowRISC offers a generous benefits package including:

• 25 days annual leave plus 8 bank holidays
• 12.5% employer’s pension contribution (subject to employee salary sacrifice of 6%)
• 4 week paid sabbatical after 4 years service
• Private Medical Insurance, Group Income Protection Insurance, Critical Illness Insurance, Life Insurance
• The opportunity to attend appropriate Industry conferences and/or training

We are open to discussions about hybrid workingWe are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternityIf you need any adjustments made to the application or selection process, please let us know by emailing [email protected]

Expected salary

£62708 – 96632 per year

Location

Cambridgeshire

Job date

Sat, 04 Jan 2025 23:41:53 GMT

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