Senior Silicon Design Engineer – Memory Subsystem Design and Logic Development

Job title:

Senior Silicon Design Engineer – Memory Subsystem Design and Logic Development

Company

Advanced Micro Devices

Job description

Job Description:WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.AMD together we advance_THE ROLE:The Memory IO team is looking for passionate and experienced RTL design engineers for the development of high-speed LPDDRx, DDRx and associated ownership and development of DDR Subsystems. Be a part of the definition, design, and development phase of industry-leading Memory IP, as well as the overall memory subsystem implementation and documentation. This opportunity includes timing and floor planning of the memory subsystem across multiple product lines as well as close interaction and coordination with the DDR Subsystem verification team.Come be a part of a cutting-edge team that delivers Industry leading IP and help our experts in RTL, Firmware, BIOS and architecture teams develop leading edge Memory interfaces!THE PERSON:You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Are you looking to take on and tackle advanced engineering challenges? We are looking for open minded, flexible, innovative, and creative Engineers looking to join a new team to develop a DDR subsystem. Are you looking for a ground floor opportunity that requires being a self-starter and the ability to independently drive tasks to completion? We are also looking for strong interpersonal and communication skills – this position will be working collaboratively across the AMD organization! If this sounds like you, please apply!KEY RESPONSIBILITIES:

• Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
• Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power
• Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
• Knowledge sharing and other contributions to Platform & System Architecture
• As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests
• Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
• Excellent knowledge of System Verilog and Verilog language with respect to RTL design.
• Advanced DDR subsystem architecture, microarchitecture, development, and implementation experience.
• Excellent debug skills and knowledge of key DDR subsystem components.
• Development and maintenance of DDR Subsystem integration, documentation, timing, and floor planning through the lifecycle of pre-silicon development.
• Subsystem and block level documentation as well as timing diagrams
• In depth knowledge of standard IP interfaces, communication of interfaces, and IP interface protocol and utilization.
• Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and multi-domain simulation synchronization.
• Clock domain crossing implementation experience

PREFERRED EXPERIENCE:

• Outstanding foundation in Systems & SoC architecture, with expertise in Memory sub-system, Fabrics, CI/O subsystems, Clocks, Resets, and Security
• Experience analyzing System-level Micro-Architectural features to identify performance bottlenecks within different workloads
• Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
• Experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controller RTL design and development.
• Knowledge and experience developing SVA/OVL and synthesizable assertions.
• Experience stitching block level IP together to form subsystems.
• VCS and Zebu Emulation verification and debug experience.
• Strong knowledge of git and perforce.
• UPF experience and knowledge of power supply implementations across subsystems and writing logic and timing constraints to handle clock domain crossings

ACADEMIC CREDENTIALS:

• Bachelor’s degree in Electrical or Computer Engineering and relevant experience, or
• Master’s or PhD degree in Electrical or Computer Engineering with relevant experience.

LOCATION:

• Vancouver, CA
• Ottawa/Markham

#LI-SH1#HYBRIDBenefits offered are described: .AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Expected salary

Location

Vancouver, BC

Job date

Tue, 09 Apr 2024 03:56:01 GMT

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