Senior Staff Engineer, Digital IC Design

Job title:

Senior Staff Engineer, Digital IC Design

Company

Semtech

Job description

Location: Bristol, UKOur Team: Semtech Corporation (NASDAQ:SMTC; www.Semtech.com) is a leading supplier of high-quality analog and mixed-signal semiconductor products. Semtech has a large number of design centres around the world, including three within the UK. The Bristol design centre is focused on optoelectronic ICs primarily targeted to datacoms and adjacent markets. Products include TIAs, laser drivers, optical receivers and fully integrated transceiver IC products from below 1Gbps to over 800Gbps. Within the centre, all functions of product development from initial ideas to full prodization take place, including, marketing, definition, design, layout, product engineering, validation, test engineering, characterization, qualification, applications, etc. Due to the significant innovation and differentiation in the development of our products, Semtech has continued to be the leader in our target markets.Job Summary:As a member of the UK Digital R&D team, the Senior Staff Engineer, Digital IC Design will work on the next generation mixed signal optical devices for Semtech’s Signal Integrity Products (SIP) team. Responsibilities include working closely with product definition team, helping define chip architecture, writing detailed design specifications, front-end RTL design and simulation, complex behavioural modelling, design Synthesis, Place and Route and DFT (Design For Test) among others. This position requires someone with a high energy level, self-motivated, with excellent communication skills and ability to work well as a part of a highly skilled development team.Responsibilities:Work closely with product definition team on developing high level requirements for products.Interpret high level design requirements or architecture documents and create detailed design specifications.Generate RTL (Register Transfer Level), block/top level simulations and timing constraints.Create thorough verification plans and fully verify designs through simulation.Behavioural modelling of complex analogue functions.Synthesis, Place and Route, DFT insertion, timing closure and ATPG (Automatic Test Pattern Generation) for SCAN test.Work closely with layout engineers to ensure design is LVS (Layout vs. Schematic), DRC (Design Rule Check) and timing clean.Ability to work with other members of the multi-discipline team to ensure the design meets all customer requirements under tight timescales.Contribute to the design verification environment definition, implementation and debugging as required.Mentor other team members.Minimum Qualifications:BSc/MSc/BEng/MEng/PhD in related fields.8+ years of related experience.Experienced in digital IC design flow from specification to tape-out.Skilled in Verilog/VHDL for design and simulation/verification is essential.Experience of energy efficient low-power logic design.Knowledge of scripting languages such as Perl, TCL etc.Expertise with digital design tools for synthesis, place and route, timing closure, equivalency checking, DFT insertion and ECO from Synopsys or Cadence.Proven track record with multiple designs in mass production.Desired QualificationsExperience with verification using high abstraction languages such as SystemVerilog, C, Vera would be an asset.Experience with mixed signal analogue/digital verification would be advantageous.FPGA design experience would be advantageous.Prior experience in designs using advanced CMOS process technologies from 180nm down to 28nm and below would be beneficial.The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.

Expected salary

Location

Bristol Area

Job date

Sun, 01 Sep 2024 07:36:58 GMT

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