SoC Design Verification Lead

Job title:

SoC Design Verification Lead

Company

Intel

Job description

Job Details:Job Description:Data Center and AI Xeon SOC Engineering group is looking for a senior pre-silicon verification lead/architect who has prior experience with SOC validation and/or complex IP/ASIC validation, from inception to product delivery to customer. Candidate must have proven track record of proficiency in industry standard validation methodologies, tools/flows, hands on UVM/SV development, test strategies, debug and disciplined execution. Individual is expected to have strong leadership skills and will be expected to lead by example, to help build high performing validation team. Experienced in VIP integration, architecting and developing validation flows, testbenches, testcases, driving reviews and effectively working with internal and external partners to resolve issues to closure and improve validation quality. Robust understanding of cache coherency and basic understanding of power management, reliability and survivability and security features is required.You will be responsible for, but not limited to:

• Architecture, development and integration of layered Verification IPs, UVM/SV testbenches, test plans and test suite to validate the integrity and quality of VIPs, compliance with standards and SoC architecture & micro-architecture requirements. Applies pre-silicon validation BKMs and methodologies in execution. Work with VIP external vendors to resolve issues within the constraints of the contract.
• Deliver validated VIP based SoC validation platform, modeling the SoC, for die level verification. Provides prompt and quality customer support to users.
• Perform functional logic verification of an integrated SoC to ensure design will meet specifications.
• Defines and develops scalable and reusable components, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and conform to microarchitecture specifications.
• Manage and execute verification plans and defines and runs system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, verification experts, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Document verification architecture, micro-architecture, and test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products.
• Demonstrate technical leadership, lead engineering team and provide status updates to leadership.

Qualifications:Minimum Qualifications:

• Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of combined technical experience listed below:

• Related technical experience should be in/with: Pre-Silicon Validation/Verification using Industry standard verification methodologies, tools, and best practices to meet time-to-market.
• Design Verification with planning, architecture, development, maintenance, and execution on complex IPs and/or SOCs.
• Proficiency in UVM/SV constrained-random coverage-based design verification.
• UVM/SV Verification IP architecture, development and validation hands on experience.
• Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols – transaction layer, data link layer, and PHY layer.
• Experience with one or more scripting languages to facilitate automation.

Preferred Qualifications:​

• Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market.
• The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
• Developing validation testbenches and test suites and driving continuous improvement into existing validation test suites and methodologies.
• Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.
• Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks.

Job Type: Experienced HireShift: Shift 1 (United States of America)Primary Location: US, Massachusetts, Beaver BrookAdditional Locations: US, California, Folsom, US, California, Santa Clara, US, Oregon, HillsboroBusiness group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust N/ABenefits:We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:Annual Salary Range for jobs which could be performed in the US:$161,230.00-$227,620.00Salary range dependent on a number of factors including location and experience.Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Expected salary

Location

United Kingdom – USA

Job date

Sat, 08 Mar 2025 07:20:43 GMT

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