FPGA Design & Formal Verification Engineer

Job title:

FPGA Design & Formal Verification Engineer

Company

Advanced Micro Devices

Job description

Job Description:WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.AMD together we advance_THE ROLE:The Advance Formal Verification team is dedicated to formal verification. It provides formal functional and security verification for a broad range of IPs including input-output virtualization, PCIe Root-Complex/End-Point, inter-chiplet highspeed connections, etc. We are currently looking for formal verification engineers with expertise in IP verification, formal verification methodologies, highspeed IO bus protocols and team leadership to take on the challenges.In these highly visible roles, the qualified candidates will use cutting edge formal verification technologies to verify the newest IPs resulting in a level of design quality not paralleled by classical verification.THE PERSON:In these highly visible roles, the qualified candidates will use cutting edge formal verification technologies to verify the newest IPs resulting in a level of design quality not paralleled by classical verification.KEY RESPONSIBILITIES:

• Collaborating with architects and designers to understand the design intents.
• Creating and executing formal verification plans for design blocks.
• Writing and debugging properties to verify the design, analyzing signatures and pushing for the resolution.
• Optimizing runtime using formal techniques.
• Collecting and reporting status and progress.
• Improving formal setups based on feedbacks from reviews, metrics, etc.
• For senior level positions:

• Leading and coordinating verification activities for a small team.
• Training and couching junior engineers.
• Developing working procedures, flows and infra.
• Handling complicated formal problems.

PREFERRED EXPERIENCE:

• Design and implement FPGA based digital systems
• Proficiency with FPGA designs in Verilog/ SystemVerilog/ VHDL
• Experience with in-system debugging of FPGAs is preferred
• Strong verification experience is required in either ASIC or FPGA.
• Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods.
• Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign-off and commercial formal tools (VC-Formal, JasperGold, Questa Formal, etc.).
• Extensive experience verifying complex, packet or control based designs.
• Familiarity with industry standard high-speed protocols such as PCIe, CXL, SATA, USB, AXI, UCIe, etc.
• Knowledge of clock domain crossing techniques is nice to have
• Experience with verification of Hardware-Firmware interaction is highly desirable.

ACADEMIC CREDENTIALS:

• BS (or higher) degree in Electronics/Electrical or Computer Engineering desired

LOCATION: Vancouver/Calgary/Toronto/Ottawa#LI-TB2Benefits offered are described: .AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Expected salary

Location

Markham, ON

Job date

Fri, 02 May 2025 04:30:24 GMT

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